Organic light emitting diode (OLED), as a current-driven light emitting device, has been increasingly applied in high-performance display. A conventional passive matrix OLED display requires shorter driving time for a single pixel as the size thereof increases, and thus it is required to increase transient current, which increases power consumption. Meanwhile, application of large current may result in a too large voltage drop on an ITO (indium tin oxide) line and cause the working voltage of the OLED to be too high, thereby reducing the efficiency thereof. While in an active matrix OLED display, currents for OLEDs are input in a progressive scanning way through switch tubes, which can effectively solve these problems.
FIG. 1 is a conventional 2T1C pixel driving circuit comprising P-type TFTs. As shown in FIG. 1, the pixel driving circuit comprises: a switch transistor M1 configured to control input of a data line voltage Vdata, a driving transistor M2 configured to control light emitting current of an OLED, and a storage capacitor Cs configured to provide a bias voltage and a maintaining voltage for a gate of the driving transistor M2.
The above 2T1C pixel driving circuit includes, in one frame time, two working phases: a data line voltage Vdata writing phase t1 and a display maintaining phase t2.
In the writing phase t1, the line-scanning line voltage Vscan is at a low level, at this point, the switch transistor M1 is turned on, the data line voltage Vdata is written into the storage capacitor Cs through the channel between a drain and a source of the switch transistor M1 and meanwhile is applied to the gate of the driving transistor M2 (in FIG. 1, G, S and D indicate the gate, the source and the drain, respectively), as a result, the driving transistor M2 is turned on, and the supply voltage VDD drives an OLED to emit light.
In the display maintaining phase t2, the line-scanning line voltage Vscan is at a high level, the switch transistor M1 is in a turn-off state, the channel between the drain and the source thereof is turned off, and therefore, the channel between the data line voltage Vdata and the storage capacitor Cs (the gate of the driving transistor M2) is turned off. At this point, it can be considered as that there is no path for charges on the storage capacitor Cs to discharge since the switch transistor M1 is turned off, and thus the storage capacitor Cs still maintains the state in which the storage capacitor Cs was before the switch transistor M1 is turned off, that is, the voltage across two ends of the storage capacitor Cs maintains unchanged. Therefore, the driving transistor M2 is still on and keeps the OLED emitting light until the line-scanning line voltage Vscan of the next frame cycle arrives and the switch transistor is turned on again.
Here, driving current for the OLED may be represented by the following formula (1):
                              I          OLED                =                              1            2                    ⁢                                    μ              P                        ·                          C              ox                        ·                          W              L                        ·                                          (                                  Vdata                  -                  VDD                  -                                      V                    TH                                                  )                            2                                                          (        1        )            
wherein, μP is carrier mobility, COX is capacitance of a gate oxide layer, W/L is width-to-length ratio of the transistor, Vdata is data line voltage, VDD is AMOLED backplane supply voltage and is shared by all pixel units, and VTH is threshold voltage of the transistor. It can be seen that, the driving current for the OLED is related to the backplane supply voltage VDD.
In large-sized display applications, since a backplane power line has a certain resistance, and driving currents for all pixels are provided by the supply voltage VDD, supply voltage at an area closer to the supplying position of the backplane supply voltage VDD is higher than supply voltage at an area away from the supplying position of the backplane supply voltage VDD, that is, a voltage drop occurs. Since the backplane supply voltage VDD is related to the driving current, the voltage drop may result in different currents at different areas, and thus mura occurs in displaying.
In the prior art, in each pixel unit in a pixel area on an array substrate, a power wire layer and a gate layer or a source/drain layer are arranged in the same layer and parallel to each other. In this way, in addition to a portion of a display area of the pixel unit is occupied by the gate or source/drain layer, a relatively large area of the display area of the pixel unit is occupied by the power wire layer, which decreases aperture ratio of the pixel. The power wire layer cannot be formed in a lattice-like structure, which renders the power wire layer with a relatively large resistance. Further, the area occupied by the power wire layer is limited, and the conductive section of the power wire layer is limited, which also renders the power wire layer with a relatively large resistance.